Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 21-7
The baud rate is usually written using a single write. If using 8-bit writes,
writing to ESCIx_CR1[0–7] has no effect until ESCIx_CR1[8–15] is
written, since ESCIx_CR1[0–7] is temporarily buffered until
ESCIx_CR1[8–15] is written.
When parity is enabled, the RX Data parity bit is in the data register.
21.3.3.2 eSCI Control Register 2 (ESCIx_CR2)
NOTE
DMA requests are negated when in module disable mode.
Address: Base + 0x0004 Access: R/W
0123456789101112131415
R
MDIS FBR BSTP
IEB
ERR
RX
DMA
TX
DMA
BRK
13
0
BESM
13
SB
STP
00
ORIE NFIE FEIE PFIE
W
Reset0010000000000000
Figure 21-3. eSCI Control Register 2 (ESCIx_CR2)
Table 21-4. ESCIx_CR2 Field Description
Field Description
0
MDIS
Module disable. By default the module is enabled, but can be disabled by writing a 1 to this bit. DMA requests are
negated if the device is in module disable mode.
0 Module enabled
1 Module disabled
1
FBR
Fast bit error detection. Handles bit error detection on a per bit basis. If this is not enabled, bit errors are detected on
a byte basis.
2
BSTP
Bit error/physical bus error stop. Causes DMA TX requests to be suppressed, as long as the bit error and physical
bus error flags are not cleared. This stops further DMA writes, which would otherwise cause data bytes to be
interpreted as LIN header information.
3
IEBERR
Enable bit error interrupt. Generates an interrupt, when a LIN bit error is detected. For a list of interrupt enables and
flags, Refer to Table 21-21.
4
RXDMA
Activate RX DMA channel. If this bit is enabled and the eSCI has received data, it raises a DMA RX request.
5
TXDMA
Activate TX DMA channel. Whenever the eSCI is able to transmit data, it raises a DMA TX request.
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