NXP Semiconductors MPC5566 - Edma Set Enable Error Interrupt Register (EDMA_SEEIR)

Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
9-16 Freescale Semiconductor
9.2.2.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
The EDMA_SEEIR provides a simple memory-mapped mechanism to set a given bit in the
EDMA_EEIRH or EDMA_EEIRL to enable the error interrupt for a given channel. The data value on a
register write causes the corresponding bit in the EDMA_EEIRH or EDMA_EEIRL to be set. Setting bit
1 (SEEIn) provides a global set function, forcing the entire contents of EDMA_EEIRH or EDMA_EEIRL
to be asserted. Reads of this register return all zeroes.
9.2.2.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
The EDMA_CEEIR provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_EEIRH or EDMA_EEIRL to disable the error interrupt for a given channel. The data value on
a register write causes the corresponding bit in the EDMA_EEIRH or EDMA_EEIRL to be cleared.
Setting bit 1 (CEEIn) provides a global clear function, forcing the entire contents of the EDMA_EEIRH
or EDMA_EEIRL to be zeroed, disabling error interrupts for all channels. Reads of this register return
all zeroes.
Table 9-7. EDMA_CERQR Field Descriptions
Field Description
0 Reserved
1–7
CERQ[0:6]
Clear enable request.
0–63 Clear corresponding bit in EDMA_ERQRH or EDMA_ERQRL
64–127 Clear all bits in EDMA_ERQRH and EDMA_ERQRL
Address: Base + 0x001A Access: User W/O
01234567
R00000000
W SEEI[0:6]
Reset00000000
Figure 9-10. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
Table 9-8. EDMA_SEEIR Field Descriptions
Field Description
0 Reserved
1–7
SEEI[0:6]
Set enable error interrupt.
0–63 Set corresponding bit in EDMA_EEIRH or EDMA_EEIRL
64–127 Set all bits in EDMA_EEIRH or EDMA_EEIRL
Address: Base + 0x001B Access: User W/O
01234567
R00000000
W
CEEI[0:6]
Reset00000000
Figure 9-11. eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)