Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 25-83
25.17.2.11.1 NXDM JTAG DID Register
This JTAG DID register that is included in the NXDM module provides key development attributes to the
development tool concerning the NXDM block. The register is accessed through the standard JTAG IR/DR
paths. Refer to Chapter 23, “Voltage Regulator Controller (VRC) and POR Module.”
25.17.2.11.2 Enabling the NXDM TAP Controller
Assertion of a power-on-reset signal or assertion of the JCOMP pin resets all TAP controllers on the
device. Upon exit from the test-logic-reset state, the IR value is loaded with the JTAG DID. When the
NXDM TAP is accessed, this information helps the development tool obtain information about the Nexus
module it is accessing, such as version, sequence, feature set, and so forth.
25.17.2.11.3 NXDM Register Access via JTAG
Access to Nexus register resources is enabled by loading a single instruction (NEXUS_ACCESS) into the
JTAG Instruction Register (IR). This IR is part of the IEEE® 1149.1 TAP controller within the NXDM
modules. Refer to Section 24.4.4, “JTAGC Instructions.”
After the JTAG NEXUS_ACCESS instruction has been loaded, the JTAG port allows tool/target
communications with all Nexus registers according to the map in Table 25-46.
Access: R/W
313029282726252423222120191817161514131211109876543210
R PRN DC PIN MIC 1
W
Reset00000111110001100000000000011101
Figure 25-64. NXDM JTAG DID Register
Table 25-54. NXDM JTAG DID Field Descriptions
Field Description
31–28
PRN
1
1
The revision number is initially 0 and could change in the future.
Embedded part revision number (0x0)
27–22
DC
Freescale design center ID number (0x1F)
21–12
PIN
NXDM module part identification number, defines the features set. (0x60)
11–1
MIC
Manufacturer identity code
0x00E Freescale
0 Fixed per JTAG 1149.1
1 Always set
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