NXP Semiconductors MPC5566 - IRQ Rising-Edge Event Enable Register (SIU_IREER)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-20 Freescale Semiconductor
6.3.1.9 IRQ Rising-Edge Event Enable Register (SIU_IREER)
The SIU_IREER enables rising edge-triggered events on IRQ[n]. Rising- and falling-edge events are
enabled by setting the bits in SIU_IREER and SIU_IFEER.
The following table describes the fields in the IRQ rising-edge event enable register:
6.3.1.10 IRQ Falling-Edge Event Enable Register (SIU_IFEER)
The SIU_IFEER enables falling edge-triggered events on IRQ[n]. Rising- and falling-edge events are
enabled by setting the bits in both SIU_IREER and SIU_IFEER.
Address: Base + 0x0028 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 0 0 0 0 0 0000000000
W
Reset0 0 0 0 0 0 0000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IREE
15
IREE
14
IREE
13
IREE
12
IREE
11
IREE
10
IREE
9
IREE
8
IREE
7
IREE
6
IREE
5
IREE
4
IREE
3
IREE
2
IREE
1
IREE
0
W
Reset0 0 0 0 0 0 0000000000
Figure 6-10. IRQ Rising-Edge Event Enable Register (SIU_IREER)
Table 6-16. SIU_IREER Field Descriptions
Field Function
0–15 Reserved
16–31
IREEn
IRQ rising-edge event enable n. Enables rising-edge-triggered events on the corresponding IRQ[n] pin.
0 Rising-edge event is disabled.
1 Rising-edge event is enabled.
Address: Base + 0x002C Access: R/W
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IFEE
15
IFEE
14
IFEE
13
IFEE
12
IFEE
11
IFEE
10
IFEE
9
IFEE
8
IFEE
7
IFEE
6
IFEE
5
IFEE
4
IFEE
3
IFEE
2
IFEE
1
IFEE
0
W
Reset0000000000000000
Figure 6-11. IRQ Falling-Edge Event Enable Register (SIU_IFEER)