Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-48 Freescale Semiconductor
NOTE
Whenever the software driver sets an E bit in one or more receive
descriptors, the driver must follow that with a write to RDAR.
15.5.3 Ethernet Transmit Buffer Descriptor (TxBD)
Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs.
The Ethernet controller confirms transmission by clearing the ready bit (R bit) when DMA of the buffer is
complete. In the TxBD the application initializes the R, W, L, and TC bits and the length (in bytes) in the
first word, and the buffer pointer in the second word.
The FEC sets the R bit = 0 in the first word of the BD when the buffer has been DMA’d. Status bits for the
buffer/frame are not included in the transmit buffer descriptors. Transmit frame status is indicated via
individual interrupt bits (error conditions) and in statistic counters in the MIB block. See Section 15.3.3,
“MIB Block Counters Memory Map” for more details.
Offset + 0 Bit 13 CR Receive CRC error. Written by the FEC. This frame contains a
CRC error and is an integral number of octets in length. This bit
is valid only if the L-bit is set.
Offset + 0 Bit 14 OV Overrun. Written by the FEC. A receive FIFO overrun occurred
during frame reception. If this bit is set, the other status bits, M,
LG, NO, CR, and CL lose their normal meaning and are
cleared to zero. This bit is valid only if the L-bit is set.
Offset + 0 Bit 15 TR Is set if the receive frame is truncated (frame length > 2047
bytes). If the TR bit is set, the frame must be discarded and the
other error bits must be ignored because their validity cannot
be verified.
Offset + 2 Bits [0:15] Data Length Data length. Written by the FEC. Data length is the number of
8-bit data groups (octets) written by the FEC into this BD’s data
buffer if L = 0 (the value is equal to EMRBR), or the length of
the frame including CRC if L = 1. It is written by the FEC once
as the BD is closed.
Offset + 4 Bits [0:15] A[0:15] RX data buffer pointer, bits [0:15]
1
Offset + 6 Bits [0:15] A[16:31] RX data buffer pointer, bits [16:31]
1
The receive buffer pointer, which contains the address of the associated data buffer, must always be evenly
divisible by 16. The buffer must reside in memory external to the FEC. This value is never modified by the
Ethernet controller.
Table 15-36. Receive Buffer Descriptor Field Definitions (continued)
Halfword Location Field Name Description
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