NXP Semiconductors MPC5566 - Etpu Channel Data Transfer Request Enable Register (ETPU_CDTRER)

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
18-38 Freescale Semiconductor
18.4.5.6 eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)
Data transfer request enable status bits from all channels are grouped in ETPU_CDTRER. The bits are
mirrored in the channels’ configuration registers. For more on configuration registers and data transfer
request enable, refer to Section 18.4.6.2, “eTPU Channel n Configuration Register (ETPU_CnCR),” and
the eTPU Reference Manual.
Address: Base + 0x0000_0240 (eTPU A)
Address: Base + 0x0000_0244 (eTPU B)
Access: R/W
0123456789101112131415
R
CIE
31
CIE
30
CIE
29
CIE
28
CIE
27
CIE
26
CIE
25
CIE
24
CIE
23
CIE
22
CIE
21
CIE
20
CIE
19
CIE
18
CIE
17
CIE
16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CIE
15
CIE
14
CIE
13
CIE
12
CIE
11
CIE
10
CIE
9
CIE
8
CIE
7
CIE
6
CIE
5
CIE
4
CIE
3
CIE
2
CIE
1
CIE
0
W
Reset0000000000000000
Figure 18-18. eTPU Channel Interrupt Enable Register (ETPU_CIER)
Table 18-19. ETPU_CIER Field Descriptions
Field Description
0–31
CIEn
Channel n interrupt enable. Enable the eTPU channels to interrupt the MPC5566 core.
0 Interrupt disabled for channel n.
1 Interrupt enabled for channel n
For details about interrupts refer to the eTPU Reference Manual.
Address: Base + 0x0000_0250 (eTPU A)
Address: Base + 0x0000_0254 (eTPU B)
Access: R/W
0123456789101112131415
R
DTRE
31
DTRE
30
DTRE
29
DTRE
28
DTRE
27
DTRE
26
DTRE
25
DTRE
24
DTRE
23
DTRE
22
DTRE
21
DTRE
20
DTRE
19
DTRE
18
DTRE
17
DTRE
16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DTRE
15
DTRE
14
DTRE
13
DTRE
12
DTRE
11
DTRE
10
DTRE
9
DTRE
8
DTRE
7
DTRE
6
DTRE
5
DTRE
4
DTRE
3
DTRE
2
DTRE
1
DTRE
0
W
Reset0000000000000000
Figure 18-19. eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)