Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 21-17
21.3.3.8 LIN CRC Polynomial Register (ESCIx_LPR)
ESCIx_LPRn can be written when there are no ongoing transmissions.
Address: Base + 0x0014 Access: R/O
0123456789101112131415
RD7D6 D5D4D3D2D1D000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W
Reset0000000000000000
Figure 21-9. LIN Receive Register (ESCIx_LRR)
Table 21-13. ESCIx_LRR Field Descriptions
Field Description
0–7
Dn
Data bit n. Provides received data bytes from RX frames. Data is only valid when the ESCIx_SR[RXRDY] flag is set.
CRC and checksum information are not available in the ESCIx_LRR unless they are treated as data. It is possible
to treat CRC and checksum bytes as data by deactivating the CSUM respectively CRC control bits in the ESCIx_LTR;
however, then CRC and CSUM checking has to be performed by software.
Data bytes must be read from the ESCIx_LRR (by CPU or DMA) before any new bytes (including CRC or checksum)
are received from the LIN bus otherwise the data byte is lost and OVFL is set.
Note: The data must be collected and the LIN frame finished (including CRC and checksum if applicable) before a
wake-up character can be sent.
8–31 Reserved.
Address: Base + 0x0018 Access: R/W
0123456789101112131415
R
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
W
Reset1100010110011001
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W
Reset0000000000000000
Figure 21-10. LIN CRC Polynomial Register (ESCIx_LPR)
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