NXP Semiconductors MPC5566 - Chapter 10; INTC Current Priority Register (INTC_CPR)

Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 10-11
10.3.1.2 INTC Current Priority Register (INTC_CPR)
The INTC_CPR masks any peripheral or software settable interrupt request set at the same or lower
priority as the current value of the INTC_CPR[PRI] field from generating an interrupt request to the
processor. When the INTC interrupt acknowledge register (INTC_IACKR) is read in software vector
mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the
value of PRI is pushed onto the LIFO, and PRI is updated with the priority of the preempting interrupt
request. When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the
INTC_CPR’s PRI field.
The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to
Section 10.5.5, “Priority Ceiling Protocol.”
NOTE
On some Power Architecture MCUs, a store to raise the PRI field which
closely precedes an access to a shared resource can result in a non-coherent
access to that resource unless an mbar or msync followed by an isync
sequence of instructions is executed between the accesses. An mbar or
msync instruction is also necessary after accessing the resource but before
lowering the PRI field. Refer to Section 10.5.5.2, “Ensuring Coherency.”
10.3.1.3 INTC Interrupt Acknowledge Register (INTC_IACKR)
The INTC_IACKR provides a value that can be used to load the address of an ISR from a vector table. The
vector table can be composed of addresses of the ISRs specific to their respective interrupt vectors.
In software vector mode, reading the INTC_IACKR acknowledges the INTC's interrupt request. Refer to
Section 10.1.4.1, “Software Vector Mode” for a detailed description of the effect on the interrupt request
to the processor. The reading also pushes the PRI value in the INTC current priority register (INTC_CPR)
onto the LIFO and updates PRI in the INTC_CPR with the priority of the interrupt request. The side effect
Address: Base + 0x0008 (INTC_CPR) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 00000000000000000000000
PRI
W
Reset00000000000000000000000000001111
Figure 10-8. INTC Current Priority Register (INTC_CPR)
Table 10-5. INTC_CPR Field Descriptions
Field Description
0–27 Reserved, must be cleared.
28–31
PRI
Priority. PRI is the priority of the currently executing ISR according to the field values defined below.
1111 Priority 15 (highest)
1110 Priority 14
...
0001 Priority 1
0000 Priority 0 (lowest)