Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-37
19.3.3.1 ADCn Control Registers (ADC0_CR and ADC1_CR)
The ADCn control registers (ADCn_CR) are used to configure the on-chip ADCs.
0x0002 ADC Time Stamp Control Register (ADC_TSCR)
1
Write/Read
0x0003 ADC Time Base Counter Register (ADC_TBCR)
1
Write/Read
0x0004 ADC1 Gain Calibration Constant Register (ADC1_GCCR) Write/Read
0x0005 ADC1 Offset Calibration Constant Register (ADC1_OCCR) Write/Read
0x0006–0x00FF Reserved —
1
This register is also accessible by configuration commands sent to the ADC0 command buffer.
Address: 0x0001 Access: R/W
0123456789101112131415
RADC0
_EN
000
ADC0_
EMUX
000000 ADC0_CLK_PS
W
Reset0000000000011111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RADC1
_EN
000
ADC1_
EMUX
000000 ADC1_CLK_PS
W
Reset0000000000011111
Figure 19-19. ADCn Control Registers (ADC0_CR and ADC1_CR)
Table 19-27. ADCn_CR Field Descriptions
Field Description
0
ADCn_
EN
ADCn enable. Enables ADCn to perform A/D conversions. Refer to Section 19.4.5.1, “Enabling and Disabling the
on-chip ADCs,” for details.
0 ADC is disabled. Clock supply to ADC0/1 is stopped.
1 ADC is enabled and ready to perform A/D conversions.
Note: The bias generator circuit inside the ADC ceases functioning when both ADC0_EN and ADC1_EN bits are
negated.
Note: Conversion commands sent to a disabled ADC are ignored by the ADC control hardware.
Note: When the ADCn_EN status is changed from asserted to negated, the ADC clock does not stop until it reaches
its low phase.
1–3 Reserved.
Table 19-26. ADC1 Registers (continued)
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