Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-38 Freescale Semiconductor
4
ADCn_
EMUX
ADCn external multiplexer enable. When ADCn_EMUX is asserted, the MA pins output digital values to the external
channel number selected to convert external multiplexer inputs. Refer to Section 19.4.6, “Internal/External
Multiplexing,” for a detailed description about how ADCn_EMUX affects channel number decoding.
0 External multiplexer disabled; no external multiplexer channels can be selected.
1 External multiplexer enabled; external multiplexer channels can be selected.
Note: Both ADCn_EMUX bits must not be asserted at the same time.
Note: The ADCn_EMUX bit must only be written when the ADCn_EN bit is negated. ADCn_EMUX can be set during
the same write cycle used to set ADCn_EN.
5–10 Reserved.
11–15
ADCn_
CLK_PS
[0:4]
ADCn clock prescaler. The ADCn_CLK_PS field controls the system clock divide factor for the ADCn clock as in
Ta bl e 1 9- 28. Refer to Section 19.4.5.2, “ADC Clock and Conversion Speed,” for details about how to set
ADC0/1_CLK_PS.
The ADCn_CLK_PS field must only be written when the ADCn_EN bit is negated. This field can be configured during
the same write cycle used to set ADCn_EN.
Table 19-28. System Clock Divide Factor for ADC Clock
ADCn_CLK_PS[0:4]
System Clock
Divide Factor
0b00000 2
0b00001 4
0b00010 6
0b00011 8
0b00100 10
0b00101 12
0b00110 14
0b00111 16
0b01000 18
0b01001 20
0b01010 22
0b01011 24
0b01100 26
0b01101 28
0b01110 30
0b01111 32
0b10000 34
0b10001 36
0b10010 38
Table 19-27. ADCn_CR Field Descriptions (continued)
Field Description
To Next Page
Loading...
