e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 3-19
3.3.1.5.3 MAS[2] Register
The MAS[2] register is shown in Figure 3-9.
MAS[2] fields are defined in Table 3-5.
20–23
TSIZE
Entry page size.
Supported page sizes are:
0001 4 KB 0110 4 MB
0010 16 KB 0111 16 MB
0011 64 KB 1000 64 MB
0100 256 KB 1001 256 MB
0101 1 MB
All other values are undefined.
24–31 Reserved, must be cleared.
SPR: 626 Access: R/W
012345678910111213141516171819202122232425262728293031
R
EPN —
V
L
E
WIMGE
W
Reset Undefined on Power Up ⎯ Unchanged on Reset
Figure 3-9. MMU Assist Register 2 — MAS[2]
Table 3-5. MAS[2] — EPN and Page Attributes
Field Description
0–19
EPN
Effective page number [0:19].
20–25 Reserved, must be cleared.
26
VLE
Power Architecture VLE.
0 This page is a standard Book E page.
1 This page is a Power Architecture VLE page.
27
W
Write-through required.
0 This page is considered write-back with respect to the caches in the system.
1 All stores performed to this page are written through to main memory.
28
I
Cache inhibited.
0 This page is considered cacheable.
1 This page is considered cache-inhibited.
29
M
Memory coherence required.The e200z6 does not
support the memory coherence required attribute, and thus it is
ignored.
0 Memory coherence is not required.
1 Memory coherence is required.
Table 3-4. MAS[1] — Descriptor Context and Configuration Control (continued)
Field Description
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