NXP Semiconductors MPC5566 - EBI Transfer Error Status Register (EBI_TESR)

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-16 Freescale Semiconductor
12.3.1.4 EBI Transfer Error Status Register (EBI_TESR)
The EBI_TESR contains a bit for each type of transfer error on the external bus. A bit set to logic 1
indicates what type of transfer error occurred since the last time the bits were cleared. Each bit can be
cleared by reset or by writing a 1 to it. Writing a 0 has no effect.
This register is not writable in module disable mode due to the use of power saving clock modes.
25
MDIS
Module disable mode. Allows the clock to be stopped to the non-memory mapped logic in the EBI, effectively putting
the EBI in a software controlled power-saving state. See Section 12.1.4.3, “Module Disable Mode,” for more
information. No external bus accesses can be performed when the EBI is in module disable mode (MDIS = 1).
0 Module disable mode inactive
1 Module disable mode active
26–30 Reserved.
31
DBM
Data bus mode. Controls whether the EBI is in 32-bit or 16-bit data bus mode.
0 32-bit data bus mode
1 16-bit data bus mode
Base + 0x0008 Access: R/W1c
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000000000TEAFBMTF
W w1c w1c
Reset0000000000000000
Figure 12-3. EBI Transfer Error Status Register (EBI_TESR)
Table 12-7. EBI_MCR Field Descriptions (continued)
Field Description