NXP Semiconductors MPC5566 - Negating an Interrupt Request Outside of Its ISR

Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
10-40 Freescale Semiconductor
10.5.9 Negating an Interrupt Request Outside of its ISR
10.5.9.1 Negating an Interrupt Request as a Side Effect of an ISR
Some peripherals have flag bits which can be cleared as a side effect of servicing a peripheral interrupt
request. For example, reading a specific register can clear the flag bits, and consequently their
corresponding interrupt requests too. This clearing as a side effect of servicing a peripheral interrupt
request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request
whose ISR presently is executing. This negating of a peripheral interrupt request outside of its ISR can be
a desired effect.
10.5.9.2 Negating Multiple Interrupt Requests in One ISR
An ISR can clear other flag bits besides its own flag bit. One reason that an ISR clears multiple flag bits
is because it serviced those other flag bits, and therefore the ISRs for these other flag bits do not need to
be executed.
10.5.9.3 Proper Setting of Interrupt Request Priority
Whether an interrupt request negates outside of its own ISR due to the side effect of an ISR execution or
the intentional clearing a flag bit, the priorities of the peripheral or software settable interrupt requests for
these other flag bits must be selected properly. Their PRIn values in INTC priority select registers
(INTC_PSR0–INTC_PSR329) must be selected to be at or lower than the priority of the ISR that cleared
their flag bits. Otherwise, those flag bits still can cause the interrupt request to the processor to assert.
Furthermore, the clearing of these other flag bits also has the same timing relationship to the writing to
INTC end-of-interrupt register (INTC_EOIR) as the clearing of the flag bit that caused the present ISR to
be executed. Refer to Section 10.4.3.1.2, “End-of-Interrupt Exception Handler,” for more information.
A flag bit whose enable bit or mask bit is negating its peripheral interrupt request can be cleared at any
time, regardless of the peripheral interrupt request’s PRIn value in INTC_PSRn.
10.5.10 Examining LIFO contents
Normally you do not need to know the contents of the LIFO, or even how deep the LIFO is nested.
Although the LIFO contents are not memory mapped, you can read the contents by popping the LIFO and
reading the PRI field in the INTC current priority register (INTC_CPR). Disabling processor recognition
of interrupts while examining the LIFO contents provides a coherent view of the preempted priorities.
The code sequence is:
pop_lifo:
store to INTC_EOIR
load INTC_CPR, examine PRI, and store onto stack
if PRI is not zero or value when interrupts were enabled, branch to pop_lifo