Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
25-20 Freescale Semiconductor
The IEEE® 1149.1-2001 specification may be ordered for further detail on electrical and pin protocol
compliance requirements.
The NPC implements a Nexus controller state machine that transitions based on the state of the IEEE®
1149.1-2001 state machine shown in Figure 25-5. The Nexus controller state machine is defined by the
IEEE-ISTO 5001-2003 standard. It is shown in Figure 25-10.
The instructions implemented by the NPC TAP controller are listed in Table 25-14. The value of the
NEXUS-ENABLE instruction is 0b0000. Each unimplemented instruction acts like the BYPASS
instruction. The size of the NPC instruction register is 4-bits.
Data is shifted between TDI and TDO starting with the least significant bit as illustrated in Figure 25-8.
This applies for the instruction register and all Nexus tool-mapped registers.
Figure 25-8. Shifting Data Into a Register
25.7.2.3.1 Enabling the NPC TAP Controller
Assertion of the power-on reset signal, entry into censored mode, or negating JCOMP resets the NPC TAP
controller. When not in power-on reset or censored mode, the NPC TAP controller is enabled by asserting
JCOMP and loading the ACCESS_AUX_TAP_NPC instruction in the JTAGC. Loading the
NEXUS-ENABLE instruction then grants access to NPC registers.
Table 25-14. Implemented Instructions
Instruction Name Private/Public Opcode Description
NEXUS-ENABLE Public 0x0
Activate Nexus controller state machine to read and
write NPC registers.
BYPASS Private 0xF
NPC BYPASS instruction. Also the value loaded into
the NPC IR upon exit of reset.
Selected register TDOTDI
MSB LSB
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