Signal Description
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 2-19
2.3.1 Reset and Configuration Signals
2.3.1.1 External Reset Input
RESET
The RESET input is asserted by an external device to reset the all modules of the device MCU. The RESET
pin must be asserted during a power-on reset.
Read Section 4.2.1, “Reset Input (RESET).”
2.3.1.2 External Reset Output
RSTOUT
The RSTOUT output is a push/pull output that is asserted during an internal device reset. The pin can also
be asserted by software without causing an internal reset of the device MCU.
Read Section 4.2.2, “Reset Output (RSTOUT).”
NOTE
During a power-on-reset (POR), RSTOUT is tri-stated.
2.3.1.3 Phase Locked-Loop Configuration / External Interrupt Request / GPIO
PLLCFG[0]_IRQ
[4]_GPIO[208]
PLLCFG[0]_IRQ[4]_GPIO[208] are sampled on the negation of the RESET input pin, if the RSTCFG pin
is asserted at that time. The values are used to configure the FMPLL mode of operation. The alternate
function is an external interrupt request input.
2.3.1.4 Phase Locked-Loop Configuration / External Interrupt Request / DSPI /
GPIO
PLLCFG[1]_IRQ
[5]_SOUTD_GPIO[209]
PLLCFG[1]_IRQ[5]_SOUTD_GPIO[209] — If the RSTCFG signal is asserted, these functions are
sampled at that time when the RESET
input pin negates. The values are used to configure the FMPLL
operation mode. The alternate function is an external interrupt request input, and the second alternate
function is the data output for the DSPI module D.
2.3.1.5 Phase Locked-Loop Configuration
PLLCFG[2]
The MPC5566 does not use PLLCFG[2], therefore PLLCFG[2] is tied low.
Read Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR).”
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