NXP Semiconductors MPC5566 - Loss-Of-Clock Reset

Reset
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 4-9
4.4.2.3.4 Loss-of-Clock Reset
A loss-of-clock reset occurs when the FMPLL detects a failure in either the reference signal or FMPLL
output, and the loss-of-clock reset enable (LOCRE) bit in the FMPLL_SYNCR is set.
The device comes out of loss-of-clock reset using the following sequence:
1. Starting the internal reset signal asserts, as indicated by RSTOUT
asserting, the value on the
WKPCFG pin is applied. At the same time, the PLLCFG[0:1] values are applied only if RSTCFG
is asserted.
2. After the FMPLL has a clock and is locked, the reset controller waits the predetermined clock
cycles before negating RSTOUT.When the clock count finishes, WKPCFG and BOOTCFG[0:1]
are sampled. BOOTCFG[0:1] is only sampled if RSTCFG asserts.
3. The reset controller then waits four clock cycles before negating RSTOUT and updating the fields
in SIU_RSR. The LCRS bit is set, and all other reset status bits in the SIU_RSR are cleared.
Refer to Section 4.2.2, “Reset Output (RSTOUT)”
Refer to Section 11.4.2.6, “Loss-of-Clock Detection,” for more information on loss-of-clock.
4.4.2.3.5 Watchdog Timer/Debug Reset
The WDRS bit in the reset status register (SIU_RSR) is set when the watchdog timer or a debug request
reset occurs.
A watchdog timer reset occurs and the WDRS bit is set when all the following conditions occur:
• e200z6 core watchdog timer is enabled with the enable next watchdog timer (EWT)
• Watchdog timer interrupt status (WIS) bits are set in the timer status register (TSR)
• Watchdog reset control (WRC) field in the timer control register (TCR) is configured to reset
• Time-out occurs
The debug tool can issue a debug reset command by writing 2’b10 to the RST bit {DBCR0[2:3]} register
in the e200z6 core, which sets the WDRS bit in the reset status register of the systems integration unit
(SIU_RSR).
To determine if WDRS was set by a watchdog timer or debug reset, check the WRS field in the e200z6
core TSR.
The effect of a watchdog timer or debug reset request is the same on the reset controller.
The debug tool can also reset the device using one of the following methods:
• Debug tool asserts the RESET
signal on the RESET_b pin
• Debug tool sets the software system reset (SSR) bit in the system reset control register
(SIU_SRCR)
The debug tool writes a one to the software external reset (SER) bit in the system reset control register
(SIU_SRCR) to generate an external software reset.