NXP Semiconductors MPC5566 - E200 Z6 Core Complex Features Not Supported in the Device

e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 3-13
• Cache registers
— L1 cache configuration register (L1CFG0) is a read-only register that allows software to query
the configuration of the L1 cache.
— L1 cache control and status register (L1CSR0) controls the operation of the L1 unified cache
such as cache enabling, cache invalidation, cache locking, enabling 4 or 8 data/instruction
ways, and control over cache power utilization, etc.
— L1 cache flush and invalidate register (L1FINV0) controls software flushing and invalidation
of the L1 unified cache.
• Memory management unit registers
— MMU configuration register (MMUCFG) is a read-only register that allows software to query
the configuration of the MMU.
— MMU assist (MAS0-MAS4, MAS6) registers provide the interface to the core from the
memory management unit.
— MMU control and status register (MMUCSR0) controls invalidation of the MMU.
— TLB configuration registers (TLBCFG0, TLBCFG1) are read-only registers that allow
software to query the configuration of the TLBs.
• System version register (SVR) is a read-only and identifies the version (model) and revision level
of the system with an e200z6 processor built on the Power Architecture embedded category.
For more details about these registers, refer to the e200z6 core reference documentation.
3.2.3 e200z6 Core Complex Features Not Supported in the Device
The device implements a subset of the e200z6 core complex features. The e200z6 core complex features
that are not supported in the device are described in Table 3-1.
Table 3-1. e200z6 Features Not Supported in the Device Core
Function / Category Description
Disabled events The external debug event (DEVT2) and unconditional debug event (UDE) are not supported.
Power management e200z6 core halted state and stopped state are not supported.
Power management The following low-power modes are not supported:
Doze mode
Nap mode
Sleep mode
Time-base interrupt wake-up from low-power mode is not supported.
Power management Core wake up is not supported.
MSR[WE] bit in the machine state register is not supported.
The OCR[WKUP] bit in the e200z6 OnCE control register (OCR) has no effect.
Machine check The machine check input pin is not supported. HID0 [EMCP] has no effect, and MCSR[MCP]
always reads a negated value.