NXP Semiconductors MPC5566 - Pad Configuration Registers 203-204 (SIU_PCR203-SIU_PCR204)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-87
Refer to Table 6-19 for bit field definitions. Table 6-112 lists the PA fields for
EMIOS[23]_ETPUB[7]_GPIO[202].
6.3.1.113 Pad Configuration Registers 203–204 (SIU_PCR203–SIU_PCR204)
The SIU_PCR203–SIU_PCR204 registers control the function, direction, and electrical attributes of
EMIOS[14:15]_GPIO[203:204]. Only the output functions of EMIOS[14:15] are connected. These
signals are referred to as GPIO[203:204] because other balls are named EMIOS[14:15]. The primary
function is EMIOS, however the default out of reset is GPIO. These signals are not affected by WKPCFG.
Figure 6-114. EMIOS[14:15]_GPIO[203:204] Pad Configuration Registers (SIU_PCR203–SIU_PCR204)
Refer to Table 6-19 for bit field definitions. Table 6-113 lists the PA fields for
EMIOS[14:15]_GPIO[203:204].
6.3.1.114 Pad Configuration Register 205 (SIU_PCR205)
The SIU_PCR205 register controls the direction and electrical attributes of the GPIO[205] pin. This
register is separate from the PCRs for GPIO[206:207] since GPIO[205] is a medium pad type with slew
Table 6-112. PCR202 PA Field Definitions
PA Field Pin Function
0b00 GPIO[202]
0b01 EMIOS[23]
0b10 ETPUB[7]
0b11 EMIOS[23]
Address: Base + (0x01D6–0x01D8) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0
PA OBE
1
1
When configured as EMIOS[14:15] the OBE bit has no effect. When GPIO[203:204] is configured as output, set the OBE bit
to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0
to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
0 0
ODE HYS SRC WPE WPS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Table 6-113. PCR203–PCR204 PA Field Definitions
PA Field Pin Function
0b0 GPIO[203:204]
0b1 EMIOS[14:15]