External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-60 Freescale Semiconductor
Most of the bidirectional signals shown in Figure 12-38 are only driven by the EBI when the EBI owns the
external bus. The only exceptions are the TA and TEA signals (described in Section 12.4.2.9, “Termination
Signals Protocol”) and the DATA bus, which are driven by the EBI for external master reads to internal
address space. As long as the external master device follows the same protocol for driving signals as this
EBI, there is no need to use the open drain mode of the pads configuration module for any EBI pins.
The Power Architecture storage reservation protocol is not supported by the EBI. Coherency between
multiple masters must be maintained via software techniques, such as event passing.
The EBI does not provide memory controller services to an external master that accesses shared external
memories. Each master must properly configure its own memory controller and drive its own chip selects
when sharing a memory between two masters.
The EBI does not support burst accesses from an external master; only single accesses of 8, 16, or 32 bits
can be performed.
1
12.4.2.10.1 Address Decoding for External Master Accesses
The EBI allows external masters to access internal address space when the EBI is configured for external
master mode. The external address is compared for any external master access, to determine if EBI
operation is required. Because only 24 address bits are available on the external bus, decoding logic is
required to allow an external master to access on-chip locations that have non-zero values in the upper
eight address bits. This is done by using the upper 4 external address bits (ADDR[8:11]) as a code to
determine whether the access is on-chip and if so, for which internal slave it is targeted.
NOTE
Even though the address bus has 26 bits available, only 24 bits are used for
external master accesses. External master accesses are not supported to the
Calibration bus.
The options for the address compare sequence are explained in the following bullets:
• External master access to another device — If ADDR[8] = 0, then the access is assumed to be to
another device and is ignored by the EBI.
• External master access to valid internal slave — If ADDR[8] = 1, then ADDR[9:11] are checked
versus a list of 3-bit codes to determine which internal slave to forward the access to. The upper
eight internal address bits are set appropriately by the EBI according to this 3-bit code, and internal
address bits [8:11] are set appropriately to match the internal slave selected.
• External master access to invalid internal slave — If the 3-bit code does not match a valid internal
slave, then the EBI responds with a bus error.
1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. See Section 12.4.2.11,
“Non-Chip-Select Burst in 16-bit Data Bus Mode”.
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