NXP Semiconductors MPC5566 - Eqadc CFIFO Push Registers 0-5 (Eqadc_Cfprn)

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-16 Freescale Semiconductor
19.3.2.4 eQADC CFIFO Push Registers 0–5 (EQADC_CFPRn)
The EQADC_CFPRs provide a mechanism to fill the CFIFOs with command messages from the command
queues. Refer to Section 19.4.3, “eQADC Command FIFOs,” for more information on the CFIFOs and to
Section 19.4.1.2, “Message Format in eQADC,” for a description on command message formats.
0b1011 2049 17075.00
0b1100 4097 34141.67
0b1101 8193 68275.00
0b1110 16385 136541.67
0b1111 32769 273075.00
Address: Base + 0x0010 (EQADC_CFPR0)
Base + 0x0014 (EQADC_CFPR1);
Base + 0x0018 (EQADC_CFPR2)
Base + 0x001C (EQADC_CFPR3)
Base + 0x0020 (EQADC_CFPR4)
Base + 0x0024 (EQADC_CFPR5)
Access: WO
0123456789101112131415
R0000000000000000
W CF_PUSHn
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W CF_PUSHn
Reset0000000000000000
Figure 19-5. eQADC CFIFO Push Registers 0–5 (EQADC_CFPRn)
Table 19-7. EQADC_CFPRn Field Descriptions
Field Description
0–31
CF_PUSHn
[0:31]
CFIFO push data n. When CFIFOn is not full, writing to the whole word or any bytes of EQADC_CFPRn pushes
the 32-bit CF_PUSHn value into CFIFOn. Writing to the CF_PUSHn field also increments the corresponding
CFCTRn value by one in Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn).”
When the CFIFOn is full, the eQADC ignores any write to the CF_PUSHn. Reading the EQADC_CFPRn always
returns 0.
Note: Write only whole words to the EQADC_CFPRn registers. Writing halfwords or bytes to EQADC_CFPR
pushes the entire 32-bit CF_PUSH field into the CFIFO, but undefined data fills the areas of CF_PUSH that
were not specifically designated as target locations for the write.
Table 19-6. Minimum Required Time to Valid ETRIG (continued)
DFL[0:3] Minimum Clock Count
Minimum Time (ns)
(System Clock = 120MHz)