System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-37
6.3.1.34 Pad Configuration Registers 58 (SIU_PCR58)
The SIU_PCR58 register controls the function, direction, and electrical attributes of
DATA[30]_FEC_RXD[2]_GPIO[58].
Figure 6-35. DATA[30]_FEC_RXD[2]_GPIO[58] Pad Configuration Registers (SIU_PCR58)
Refer to Table 6-19 for bit field definitions. Table 6-35 lists the PA fields for
DATA[30]_FEC_RXD[2]_GPIO[58].
6.3.1.35 Pad Configuration Registers 59 (SIU_PCR59)
The SIU_PCR59 register controls the function, direction, and electrical attributes of
DATA[31]_FEC_RXD[3]_GPIO[59].
Figure 6-36. DATA[31]_FEC_RXD[3]_GPIO[59] Pad Configuration Registers (SIU_PCR59)
Address: Base + 0x00B4 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[30] or FEC_RXD[2], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[30] or FEC_RXD[2], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[30] or FEC_RXD[2].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Table 6-35. PCR58 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[58]
0b01 DATA[30]
0b10 FEC_RXD[2]
0b11 DATA[30]
Address: Base + 0x00B6 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[31] or FEC_RXD[3], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[31] or FEC_RXD[3], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[31] or FEC_RXD[3].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
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