NXP Semiconductors MPC5566 - FBIU Per-Master Prefetch Triggering

Flash Memory
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 13-25
13.4.1.9 FBIU Per-Master Prefetch Triggering
Prefetch triggering can be controlled for individual bus masters. System bus accesses indicate the
requesting master.
13.4.1.10 FBIU Buffer Invalidation
The line read buffers can be invalidated under hardware and software control. Buffers are automatically
invalidated whenever the buffers are turned on or off, or at the beginning of a program or erase operation.
NOTE
Disable prefetching before invalidating the buffers. This includes starting a
program or erase operation, or turning on and off the buffers.
13.4.1.11 Flash Wait-state Emulation
Emulation of other memory array timings are supported by the Flash BIU. This functionality can be useful
to maintain the access timing for blocks of memory which were used to overlay flash blocks for the
purpose of system calibration or tuning during code development.
The Flash BIU inserts additional primary wait states according to user-programmable values for primary
wait states. When these inputs are non-zero, additional cycles are added to system bus transfers. Normal
system bus termination is extended. In addition, no line read buffer prefetches are initiated, and buffer hits
are ignored.
13.4.2 Flash Memory Array: User Mode
In user (normal) operating mode the flash module can be read, written (register writes and interlock
writes), programmed, or erased. The following subsections define all actions that can be performed in
normal operating mode. The registers mentioned in these sections are detailed in Section 13.3.2, “Register
Descriptions.”
13.4.2.1 Flash Read and Write
The default state of the flash module is read. The main and shadow address space can be read only in the
read state. The module configuration register (FLASH_MCR) is always available for read. The flash
module enters the read state on reset. The flash module is in the read state under four sets of conditions:
• The read state is active when FLASH_MCR[STOP] = 0 (user mode read).
• The read state is active when FLASH_MCR[PGM] = 1 and/or FLASH_MCR[ERS] = 1 and high
voltage operation is ongoing (read while write).
NOTE
Reads done to the partitions being operated on (either erased or
programmed) result in an errors and the FLASH_MCR[RWE] bit is set.