e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
3-18 Freescale Semiconductor
3.3.1.5.2 MAS[1] Register
The MAS[1] register is shown in Figure 3-8.
MAS[1] fields are defined in Table 3-4.
Table 3-3. MAS[0] — MMU Read/Write and Replacement Control
Field Description
0–1 Reserved, must be cleared.
2–3
TLBSEL
Selects TLB for access.
01 TLB1 (ignored by the e200z6, write to 01 for future compatibility)
4–10 Reserved, must be cleared.
11–15
ESEL
Entry select for TLB1.
16–26 Reserved, must be cleared.
27–31
NV
Next replacement victim for TLB1 (software managed). Software updates this field; it is copied to the ESEL field on
a TLB error.
SPR: 625 Access: R/W
0 1 2345678910111213141516171819202122232425262728293031
R
VALID IPROT
—TID—TSTSIZE —
W
Reset Undefined on Power Up ⎯ Unchanged on Reset
Figure 3-8. MMU Assist Register 1 — MAS[1]
Table 3-4. MAS[1] — Descriptor Context and Configuration Control
Field Description
0
VALID
TLB entry valid.
0 This TLB entry is invalid.
1 This TLB entry is valid.
1
IPROT
Invalidation protect
0 Entry is not protected from invalidation.
1 Entry is protected from invalidation.
Protects TLB entry from invalidation by tlbivax (TLB1 only), or flash invalidates through MMUCSR0[TLB1_FI].
2–7 Reserved, must be cleared.
8–15
TID
Translation ID bits.
This field is compared with the current process IDs of the effective address to be translated. A TID value of 0 defines
an entry as global and matches with all process IDs.
16–18 Reserved, must be cleared.
19
TS
Translation address space.
This bit is compared with the IS or DS fields of the MSR (depending on the type of access) to determine if this TLB
entry can be used for translation.
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