NXP Semiconductors MPC5566 - Pad Configuration Registers 1-3 (SIU_PCR1-SIU_PCR3)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-25
Refer to Table 6-19 for bit field definitions. Table 6-20 lists the PA values for CS[0]_ADDR[8]_GPIO[0].
6.3.1.14 Pad Configuration Registers 1–3 (SIU_PCR1–SIU_PCR3)
The SIU_PCR1–SIU_PCR3 registers control the function, direction, and electrical attributes of
CS[1:3]_ADDR[9:11]_GPIO[1:3].
Figure 6-15. CS[1:3]_ADDR[9:11]_GPIO[1:3] Pad Configuration Registers (SIU_PCR1–SIU_PCR3)
Refer to Table 6-19 for bit field definitions. Table 6-21 lists the PA values for
CS[1:3]_ADDR[9:11]_GPIO[1:3].
Table 6-20. PCR0 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[0]
0b01 CS
[0]
0b10 ADDR[8]
0b11 CS[0]
Address: Base + (0x0042–0x0046) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA
1
1
Do not configure the PA fields in PCR1–3 and PCR5–7 to select ADDR[9:11]. Configure only one set of pins to ADDR[9:11]
for the address input.
OBE
2
2
When configured as CS[1:3] or ADDR[9:11], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
3
3
When configured as CS[1:3], ADDR[9:11], or GPDO, set the IBE bit to 1 to reflect the pin state in the GPDI register. Clear the
IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
4
4
When configured as CS[1:3] or ADDR[9:11], clear the ODE bit to 0.
HYS
5
5
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
6
6
Refer to the EBI section for weak pullup settings when configured as CS[1:3] or ADDR[9:11].
WPS
6
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Table 6-21. PCR1–PCR3 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[1:3]
0b01 CS[1:3]
0b10 ADDR[9:11]
0b11 CS[1:3]