Error Correction Status Module (ECSM)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 8-15
The following table describes the RAM ECC data field in the
8.3 Initialization and Application Information
The Error Correction Code (ECC) is used to verify the contents of the internal SRAM and flash memories.
This is done by generating ECC check bits. Typically ECC check bits are calculated on writes and then
used on reads to detect and correct errors.
There are eight ECC check bits for each 64-bit data doubleword.
After Power on Reset (POR), the contents of internal SRAM is random and the corresponding ECC check
bits are unknown. To prevent generating ECC errors during reads, an initialization routine must perform
64-bit writes to all SRAM locations. Because the flash module is non-volatile, the ECC check bits are
calculated and stored when the flash is programmed.
Transparent to the application, the ECC uses the check bits to automatically correct single-bit memory
errors. Multi-bit memory errors are not correctable. If the ECC detects a multi-bit error, an exception is
generated. The type of exception generated by a multi-bit error depends on the settings of the EE and ME
in the Machine State Register (MSR), as shown in Table 8-15. When error reporting is enabled, as long as
its priority is 0, an interrupt request is generated to the interrupt controller (INTC) even though the INTC
request is not serviced.
ECSM Base + 0x006C Access: Read
0123456789101112131415
RREDL
W
Reset
1
UUUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RREDL
W
Reset
1
UUUUUUUUUUUUUUUU
1
“U” signifies a bit that is uninitialized.
Figure 8-13. RAM ECC Data Low Register (ECSM_REDRL)
Table 8-14. ECSM_REDRL Field Descriptions
Field Description
0–31
REDL
[0:31]
RAM ECC data. Contains the data associated with the faulting access of the last, correctly-enabled RAM ECC event.
The register contains the data value taken directly from the data bus. The reset value of this field is undefined.
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