Error Correction Status Module (ECSM)
MPC5566 Microcontroller Reference Manual, Rev. 2
8-16 Freescale Semiconductor
A non-correctable data ECC error executes one of the following actions, regardless of whether
non-correctable reporting is enabled:
When the device is in the checkstop state, processing is suspended and cannot resume without a reset.
When a debug request is presented to the core while it is in the checkstop state, the core temporarily exits
the checkstop state and enters debug mode. When debug mode exits, the core re-enters the checkstop state.
If the external interrupt bit in the MSR is enabled, data or instruction storage interrupts are reported when
the ECC errors are a result of CPU accesses, regardless of whether non-correctable reporting is enabled.
ECC errors generated by other masters (eDMA, etc.) do not generate data or instruction storage
exceptions, and the ECSM is used to report these errors. You must initialize the ECSM to enable
non-correctable reporting with interrupt generation to detect and report ECC interrupts from the ECSM.
Error reporting details can be independently enabled for flash memory and SRAM. To enable
non-correctable error reporting and save the error details for:
• SRAM, set the ERNCR bit in the ECSM Error Configuration Register (ECSM_ECR).
• Flash, set the EFNCR bit in ECSM_ECR.
When these bits are set and a non-correctable ECC error occurs, error information is recorded in other
ECSM registers and an interrupt request is generated on vector 9 of the interrupt controller (INTC).
• If the error was caused by a CPU data access, a data storage exception (IVOR2) is generated.
• If the error was caused by a CPU instruction access, an instruction storage exception (IVOR3) is
generated.
• If vector 9 of INTC is enabled, an external exception (IVOR4) is generated.
Table 8-15. MSR[EE] and MSR[ME] Bit Settings
Field Description
EE External interrupt enable.
0 External input interrupts disabled.
1 External interrupts enabled.
ME Machine check enable.
0 Machine check interrupts disabled. Enters machine check.
1 Machine interrupts enabled.
Table 8-16. Non-correctable Data ECC States
MSR[EE] MSR[ME] Access Type Result
0 0 Instruction or data Enters checkstop state. A reset is required to resume processing.
0 1 Instruction or data Machine check interrupt (IVOR1).
1 X Data Data storage interrupt (IVOR2). External interrupt must be enabled.
Machine check can be enabled or disabled.
1 X Instruction Instruction storage interrupt (IVOR3).
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