Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 21-25
Figure 21-15. Fast Bit Error Detection Timing Diagram
21.4.5 Receiver
Figure 21-16 illustrates the eSCI receiver.
Figure 21-16. eSCI Receiver Block Diagram
21.4.5.1 Receiver Character Length
The eSCI receiver accepts 8-bit or 9-bit data characters. The state of the M bit in eSCI control register 1
(ESCIx_CR1) determines the bit-length of data characters. When receiving 9-bit data, bit R8 in the eSCI
data register (ESCIx_DR) is the ninth bit (bit 8).
Clock
BESM13 = 0 BESM13 = 1
135791113152 4 6 8 10 12 14 16
RT Clock
Count
TX Output
Shift Reg
RX Input
Shift Reg
Compare
Sample
Points
RXD
H 8 7 6 5 4 3 2 1 0 L
11-bit Receive shift register
STOP START
MSB
BAUD divider
Bus
Clock
SBR0–SBR12
ILIE
IDLE
LOOP control
IDLE
interrupt
request
RIE
RDRF/OR
interrupt
request
RSRC
LOOPS
TXD
Internal Bus
SCI data registers
Data recovery
RAF
RE
WAKE
M
ILT
Wake-up
logic
All 1s
Parity
checking
PE
PT
NF
FE
PE
RDRF
OR
R8
RWU
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