MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-27
22.4.3.2 Reception Queue
A queue of received messages can be implemented that allows the CPU more time for servicing MBs. By
programming more than one MB with the same ID, received messages are queued into the MBs. Matching
to a range of IDs is possible by using ID acceptance masks that mask individual MBs. During the matching
algorithm, if a mask bit is asserted, then the corresponding ID bit is compared. If the mask bit is negated,
the corresponding ID bit is a don’t care.
Suppose, for example, that the second and fifth MBs in an array have the same ID, and FlexCAN starts
receiving messages with that ID. When FlexCAN receives the first message, the matching algorithm
matches it to MB number 2. The code of this MB is EMPTY, so the message is stored there. When the
second message arrives, the matching algorithm finds MB number 2 again, but it is not free to receive
1
.
Therefore, the matching process continues, finds MB number 5, and stores the message there. If yet
another message with the same ID arrives, the matching algorithm determines that no matching MBs are
free to receive the data, and overwrites the last matched MB (number 5). When this occurs, the code field
of the MB is set to OVERRUN.
A reception queue is built that orders the messages according to the value in the time stamp field that is
read by the CPU. This functionality is set by asserting the CANx_MCR[MBFEN] bit. The RXIMRn
registers are not initialized out of reset, since they reside in RAM and can only be programmed if the
MBFEN bit is asserted while the module is in freeze mode.
FlexCAN also supports an alternate masking scheme with only three mask registers (CANx_RXGMASK,
CANx_RX14MASK, and CANx_RX15MASK) for backwards compatibility. This alternate masking
scheme is enabled when CANx_MCR[MBFEN] is negated.
See Section 22.3.3.4, “RX Mask Registers.”
22.4.3.3 Self Received Frames
FlexCAN2 receives frames transmitted by itself if there exists an RX matching MB, but only if an ACK
is generated by an external node or if loop-back mode is enabled. Note also that FlexCAN does receive
frames transmitted by itself if there exists an RX matching MB, provided the MCR[SRXDIS] bit is not
asserted. If SRXDIS is asserted, FlexCAN does not store frames transmitted by itself in any MB, even if
it contains a matching MB, and no interrupt flag or interrupt signal is generated due to the frame reception.
22.4.4 Message Buffer Handling
To maintain data coherency and FlexCAN2 proper operation, the CPU must obey the rules described in
Section 22.4.2, “Transmit Process,” and Section 22.4.3, “Receive Process.” Any form of CPU accessing a
MB structure within FlexCAN2 other than those specified can cause FlexCAN2 to behave in an
unpredictable way.
Deactivation of a message buffer is a CPU action that causes that MB to be excluded from FlexCAN2
transmit or receive processes during the current match/arbitration round. Any CPU write access to a
control and status word of the MB structure deactivates that MB, excluding it from the current RX/TX
1. If, however, the CPU has read the MB2 data and released it before the next matching process at the CRC frame, then, even if
the MB2 RX code is FULL, the MB2 is free to receive and the message is stored in MB2 rather than in MB5.
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