NXP Semiconductors MPC5566 - External Reset

Reset
MPC5566 Microcontroller Reference Manual, Rev. 2
4-8 Freescale Semiconductor
and the associated bits/fields are updated in the SIU_RSR (the BOOTCFG[0:1] pins are only sampled if
RSTCFG asserts). In addition, the PORS and ERS bits are set, and all other reset status bits are cleared in
the reset status register.
Refer to Section 4.2.2, “Reset Output (RSTOUT).”
4.4.2.3.2 External Reset
When the reset controller detects assertion of the RESET pin, the internal reset signal and the RSTOUT
signal are asserted.
1. Starting when the internal reset signal asserts, as indicated by RSTOUT asserting, the value on the
WKPCFG pin is applied. At the same time, the PLLCFG[0:1] values are applied only if RSTCFG
asserts.
2. After the RESET signal negates and the FMPLL loss-of-lock request negates, the reset controller
waits the predetermined number of clock cycles. After the clock count finishes, WKPCFG and
BOOTCFG[0:1] are sampled. BOOTCFG[0:1] is only sampled if RSTCFG asserts.
3. The reset controller then waits four clock cycles before the negating RSTOUT, and updating the
fields in the SIU_RSR. The ERS bit is set, and all other reset status bits in the SIU_RSR are cleared.
Refer to Section 4.2.2, “Reset Output (RSTOUT)”.
4.4.2.3.3 Loss-of-Lock Reset
A loss-of-lock reset occurs when the FMPLL loses lock and the loss-of-lock reset enable (LOLRE) bit in
the FMPLL synthesizer control register (FMPLL_SYNCR) is set.
1. Starting when the internal reset signal asserts, as indicated by RSTOUT asserting, the value on the
WKPCFG pin is applied. At the same time, the PLLCFG[0:1] values are applied only if RSTCFG
asserts.
2. After the FMPLL locks, the reset controller waits the predetermined clock count and then samples
WKPCFG and BOOTCFG[0:1]. BOOTCFG[0:1] is only sampled if RSTCFG asserts.
3. The reset controller then waits four clock cycles before negating RSTOUT and updating the
register fields in the SIU_RSR. The LLRS bit is set, and all other reset status bits in the SIU_RSR
are cleared.
Refer to Section 4.2.2, “Reset Output (RSTOUT)”
Refer to Chapter 11, “Frequency Modulated Phase Locked Loop and System Clocks (FMPLL),”
for more information on loss-of-lock.