NXP Semiconductors MPC5566 - Edma Interrupt Request Registers (EDMA_IRQRH, EDMA_IRQRL)

Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 9-19
9.2.2.13 eDMA Interrupt Request Registers (EDMA_IRQRH, EDMA_IRQRL)
The EDMA_IRQRH and EDMA_IRQRL provide a bit map for the 64 channels signaling the presence of
an interrupt request for each channel. EDMA_IRQRH supports channels 63–32, while EDMA_IRQRL
covers channels 31–0.
The eDMA engine signals the occurrence of a programmed interrupt upon the completion of a data transfer
as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of
this register are directly routed to the interrupt controller (INTC). During the execution of the interrupt
service routine associated with any given channel, it is software’s responsibility to clear the appropriate
bit, negating the interrupt request. Typically, a write to the EDMA_CIRQR in the interrupt service routine
is used for this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the EDMA_CIRQR. On writes to the EDMA_IRQRH or EDMA_IRQRL, a 1 in any
bit position clears the corresponding channel’s interrupt request. A zero in any bit position has no affect
on the corresponding channel’s current interrupt status. The EDMA_CIRQR is provided so the interrupt
request for a single channel can easily be cleared without the need to perform a read-modify-write
sequence to the EDMA_IRQRH and EDMA_IRQRL.
Address: Base + 0x001F Access: User W/O
01234567
R00000000
W
CDSB[0:6]
Reset00000000
Figure 9-15. eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
Table 9-13. EDMA_CDSBR Field Descriptions
Field Description
0 Reserved
1–7
CDSB[0:6]
Clear DONE status bit.
0–63 Clear the corresponding channel’s DONE bit
64–127 Clear all TCD DONE bits