NXP Semiconductors MPC5566 - Descriptor Individual Upper Address Register (IAUR)

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-24 Freescale Semiconductor
Table 15-17 describes the fields and functions of the opcode and pause duration register (OPD):
15.3.4.2.14 Descriptor Individual Upper Address Register (IAUR)
The IAUR is written by the application. This register contains the upper 32 bits of the 64-bit individual
address hash table used in the address recognition process to check for possible match with the DA field
of receive frames with an individual DA. This register is not reset and must be initialized by the
application.
Address: Base + 0x00EC Access: User R/W
0 123456789101112131415
ROPCODE
W
Reset00000000000000 0 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PAUSE_DUR
W
Reset U
1
UUUUUUUUUUUU U U U
1
“U” signifies a bit that is uninitialized.
Figure 15-15. Opcode/Pause Duration Register (OPD)
Table 15-17. OPD Field Descriptions
Field Description
0–15
OPCODE
Opcode field used in PAUSE frames.
These bits are a constant, 0x0001.
16–31
PAUSE_DUR
Pause duration field used in PAUSE frames.