NXP Semiconductors MPC5566 - Pad Configuration Registers 26-27 (SIU_PCR26-SIU_PCR27)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-28 Freescale Semiconductor
6.3.1.18 Pad Configuration Registers 26–27 (SIU_PCR26–SIU_PCR27)
The SIU_PCR26–SIU_PCR27 registers control the function, direction, and electrical attributes of
ADDR[30:31]_ADDR[6:7]_GPIO[26:27].
Figure 6-19. ADDR[30:31]_ADDR[6:7]_GPIO[26:27]
Pad Configuration Registers (SIU_PCR26–SIU_PCR27)
Refer to Table 6-19 for bit field definitions. Table 6-25 lists the PA field for
ADDR[30:31]_ADDR[6:7]_GPIO[26:27].
6.3.1.19 Pad Configuration Registers 28–43 (SIU_PCR28–SIU_PCR43)
The SIU_PCR28–SIU_PCR43 registers control the function, direction, and electrical attributes of
DATA[0:15]_GPIO[28:43].
Figure 6-20. DATA[0:15]_GPIO[28:43]
Pad Configuration Registers (SIU_PCR28–SIU_PCR43)
Address: Base + (0x0074–0x0076) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as ADDR[30:31] or ADDR[6:7], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When configured as ADDR[30:31], ADDR[6:7] or GPDO, set the IBE bit to 1 to reflect the pin state in the corresponding GPDI
register. Clear the IBE to zero to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as ADDR[30:31] or ADDR[6:7], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as ADDR[30:31] or ADDR[6:7].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Table 6-25. PCR26–PCR27 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[26:27]
0b01 ADDR[30:31]
0b10 ADDR[6:7]
0b11 ADDR[30:31]
Address: Base + (0x0078–0x0096) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0
PA OBE
1
1
When configured as DATA[0:15], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When configured as DATA[0:15] or GPDO, set the IBE bit to 1 to reflect the pin state in the GPDI register.
Clear the IBE to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[0:15], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[0:15].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1