Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-113
The location of the data to be moved is indicated by the source address, and the final destination for that
data, by the destination address. The eDMA has transfer control descriptors (TCDs) containing these
addresses and other parameters used in the control of data transfers.
Refer to Section 9.2.2.17, “Transfer Control Descriptor (TCD)” for more information.
For every eDMA request issued by the eQADC, the eDMA must be configured to transfer a single
command (32-bit data) from the command queue, pointed to by the source address, to the CFIFO push
register, pointed to by the destination address. After the service of an eDMA request is completed, the
source address has to be updated to point to the next valid command. The destination address remains
unchanged. When the last command of a queue is transferred, do one of the following:
• Disable the eDMA channel. This might be desirable for CFIFOs in single scan mode.
• Update the source address to point to a valid command for the first command in the queue was
transferred (cyclic queue), or the first command of any other command queue. This is desirable for
CFIFOs in continuous scan mode, or in some cases, for CFIFOs in single-scan mode.
Refer to Chapter 9, “Enhanced Direct Memory Access (eDMA)” for details about how this functionality
is supported.
19.5.2.2 Receive Queue/RFIFO Transfers
In transfers involving receive queues and RFIFOs, the eDMA controller moves data from a single source
to a queue destination as shown in Figure 19-66. The location of the data to be moved is indicated by the
source address, and the final destination for that data, by the destination address. For every eDMA request
issued by the EQADC, the eDMA controller has to be configured to transfer a single result (16-bit data),
pointed to by the source address, from the RFIFO pop register to the receive queue, pointed to by the
destination address. After the service of an eDMA request is completed, the destination address has to be
updated to point to the location where the next 16-bit result are stored. The source address remains
unchanged. When the last expected result is written to the receive queue, do one of the following:
• Disable the eDMA channel.
• Update the destination address to point to the next location where in-coming results are stored: the
first entry of the current receive queue (cyclic queue); or the beginning of a new receive queue.
Refer to Chapter 9, “Enhanced Direct Memory Access (eDMA)” for details about how this functionality
is supported.
Figure 19-66. Receive Queue/RFIFO Interface
Result 1
Result 2
Result 3
•
Result n-1
Result n
One result transfer
per DMA request
RFPRx
Source Address
Destination Address
RFIFO Pop Register
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