External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-8 Freescale Semiconductor
12.2.1.3 Burst Data in Progress (BDIP)
BDIP is asserted by a master requesting the next data beat to follow the current data beat.
BDIP is driven by the EBI or an external master depending on the module in control of the external bus.
This signal is driven by the EBI on all EBI-mastered external burst cycles, but is only sampled by burst
mode memories that have a burst pin. See Section 12.4.2.5, “Burst Transfer.”
12.2.1.4 Clockout (CLKOUT)
CLKOUT is a general-purpose clock output signal to connect to the clock input of SDR external memories
and in some cases to the input clock of another MCU in multi-master configurations.
12.2.1.5 Chip Selects 0 through 3 (CS[0:3])
CS[n] is asserted by the master to indicate that this transaction is targeted for a particular memory bank.
The chip selects are driven by the EBI or an external master depending on who owns the external bus.
CS is driven in the same clock as the assertion of TS and valid address, and is kept valid until the cycle is
terminated. See Section 12.4.1.5, “Memory Controller with Support for Various Memory Types” for
details on chip select operation.
CS[0:3] are implemented in the 496 VertiCal assembly and the 416 package.
During a calibration bus access, the CS signals are held negated.
12.2.1.6 Output Enable (OE)
OE is used to indicate when an external memory is permitted to drive back read data. External memories
must have their data output buffers off when OE is negated. OE is only asserted for chip select accesses.
OE is driven by the EBI or an external master depending on which module owns the external bus. For read
cycles, OE is asserted one clock after TS assertion and held until the termination of the transfer. For write
cycles, OE is negated throughout the cycle.
During a calibration bus access, OE
is held negated.
12.2.1.7 Read/Write (RD_WR)
RD_WR indicates whether the current transaction is a read access or a write access.
RD_WR is driven by the EBI or an external master depending on which module owns the external bus.
RD_WR is driven in the same clock as the assertion of TS and valid address, and is kept valid until the
cycle is terminated.
During a calibration bus access, RD_WR
reflects the same value as the CAL_RD_WR signal.
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