External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-74 Freescale Semiconductor
Figure 12-51. MCU Connected to SDR Burst Memory
See Figure 12-23 for an example of the timing of a typical burst read operation to an SDR burst memory.
See Figure 12-14 for an example of the timing of a typical single write operation to SDR memory.
12.5.3 Running with Asynchronous Memories
The EBI also supports asynchronous memories. In this case, the CLKOUT, TS, and BDIP pins are not used
by the memory and bursting is not supported. However, the EBI still drives these outputs, and always
drives and latches all signals at positive edge CLKOUT (i.e., there is no asynchronous mode for the EBI).
The data timing is controlled by setting the SCY bits in the appropriate option register to the proper number
of wait states to work with the access time of the asynchronous memory, just as done for a synchronous
memory.
12.5.3.1 Example Wait State Calculation
This example applies to any chip select memory, synchronous or asynchronous.
As an example, say we have a memory with 50 ns access time, and we are running the external bus at
66 MHz (CLKOUT period: 15.2 ns). When the input data specification for the MCU is 4 ns:
Number of wait states = (access time) ÷ [(CLKOUT period) + (0 or 1; depending on setup time)]
50 ÷ 15.2 = 3 with 4.4 ns remaining (minimum of three wait states)
15.2 – 4.4 = 10.8 ns (achieved input data setup time)
Because actual input setup (10.8 ns) is greater than the input setup specification (4.0 ns), three wait states
is sufficient. If the input setup is less than 4.0 ns, use four wait states.
CLKOUT
CS[0]
TS
WE/BE[0]
ADDR[8:29]
DATA[0:31]
BDIP
OE
MCU
CK
CE
ADV
BAA*
WE**
A[0:21]
D[0:31]
OE
SDR burstable
flash or SRAM
*
Connection depending on the type of memory
Flash memories typically use one WE
signal as shown,
**
CAL_CS
[0]
***
4M x 32
(16-bit or 32-bit)
*** Not available on all devices, see the Signals chapter
RAMs use two or four
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