NXP Semiconductors MPC5566 - Full Duplex Flow Control

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-41
15.4.10 Full Duplex Flow Control
Full-duplex flow control allows the application to transmit pause frames and to detect received pause
frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.
To enable pause frame detection, the FEC must operate in full-duplex mode (TCR[FDEN] asserted) and
flow control enable (RCR[FCE]) must be asserted. The FEC detects a pause frame when the fields of the
incoming frame match the pause frame specifications, as shown in the table below. In addition, the receive
status associated with the frame must indicate that the frame is valid.
Pause frame detection is performed by the receiver and microcontroller modules. The microcontroller runs
an address recognition subroutine to detect the specified pause frame destination address, while the
receiver detects the TYPE and OPCODE pause frame fields. On detection of a pause frame, TCR[GTS] is
asserted by the FEC internally. When transmission has paused, the EIR[GRA] interrupt is asserted and the
pause timer begins to increment. Note that the pause timer makes use of the transmit backoff timer
hardware, which is used for tracking the appropriate collision backoff time in half-duplex mode. The pause
timer increments once every slot time, until OPD[PAUSE_DUR] slot times have expired. On
OPD[PAUSE_DUR] expiration, TCR[GTS] is deasserted allowing MAC data frame transmission to
resume. Note that the receive flow control pause (TCR[RFC_PAUSE]) status bit is asserted while the
transmitter is paused due to reception of a pause frame.
To transmit a pause frame, the FEC must operate in full-duplex mode and the application must assert flow
control pause (TCR[TFC_PAUSE]). On assertion of transmit flow control pause (TCR[TFC_PAUSE]),
the transmitter asserts TCR[GTS] internally. When the transmission of data frames stops, the EIR[GRA]
(graceful stop complete) interrupt asserts. Following EIR[GRA] assertion, the pause frame is transmitted.
On completion of pause frame transmission, flow control pause (TCR[TFC_PAUSE]) and TCR[GTS] are
deasserted internally.
7D:ff:ff:ff:ff:ff 0x3B 59
FD:ff:ff:ff:ff:ff 0x3C 60
DD:ff:ff:ff:ff:ff 0x3D 61
9D:ff:ff:ff:ff:ff 0x3E 62
BD:ff:ff:ff:ff:ff 0x3F 63
Table 15-35. PAUSE Frame Field Specification
48-bit Destination Address 0x0180_C200_0001 or Physical Address
48-bit Source Address Any
16-bit TYPE 0x8808
16-bit OPCODE 0x0001
16-bit PAUSE_DUR 0x0000–0xFFFF
Table 15-34. Destination Address to 6-Bit Hash (continued)
48-bit DA
6-bit Hash
(in hex)
Hash Decimal
Value