NXP Semiconductors MPC5566 - Internal Muxing and SIU Support for Serial and Parallel Chaining

Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-48 Freescale Semiconductor
20.4.4.7.1 Internal Muxing and SIU Support for Serial and Parallel Chaining
To support MTO, each DSPI in the device has multiplexers on the SINx, SSx, SCKx, and ht inputs. The
internal multiplexers are controlled by registers in the SIU block.
See Section 6.4.5.3, “Multiplexed Inputs for DSPI Multiple Transfer Operation.”
Figure 20-26 shows DSPI A and the multiplexers in the IMUX subblock of the SIU. The SOUTx,MTRIG,
SCKx and PCSx0 outputs from the other three DSPIs connect to the multiplexers on the DSPI A inputs.
DSPI B, DSPI C and DSPI D have similar multiplexers on their inputs.
Figure 20-26. DSPI A, B, C, and D Inputs for Multi-transfer Operations
The source for the SINx input of a DSPI can be a pin or the SOUTx of any of the other three DSPIs. The
source for the SSx input of a DSPI can be a pin or the PCSx[0] signal from any of the other DSPIs. The
source for the SCKx input of a DSPI can be a pin or the SCKx output of any of the other DSPIs. The source
for the hardware trigger (ht) input can be the MTRIG signal from any of the other DSPIs. The DSPI input
select register (SIU_DSR) selects the source for each DSPI SINx, SS
x, SCKx, and ht signal individually.
SCKA_GPIO[93]
DSPI B SCK
DSPI C SCK
DSPI D SCK
DSPI A
MTRIG
ht
PCS
SCK
‘0’
DSPI B PCS[4]_MTRIG
DSPI C PCS[4]_MTRIG
DSPI D PCS[4]_MTRIG
SIN
SOUT
SS
SIU_DISR[TRIGSELA]
SIU_DISR[SCKSELA]
PCSA_GPIO[96]
DSPI B PCS[0]
DSPI C PCS[0]
DSPI D PCS[0]
SINA_GPIO[94]
DSPI B SOUT
DSPI C SOUT
DSPI D SOUT
SIU_DISR[SINSELA]
SIU_DISR[SSSELA]