e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 3-5
3.1.3.4 MMU Features
The features of the MMU are as follows:
• Virtual memory support
• 32-bit virtual and physical addresses
• Eight-bit process identifier
• 32-entry fully associative TLB
• Support for nine page sizes (4, 16, 64, and 256 KB; 1, 4, 16, 64, and 256 MB)
• Entry flush protection
3.1.3.5 L1 Cache Features
The features of the cache are as follows:
• 32 KB, 4- or 8-way set associative unified cache
• Copyback and writethrough support
• Eight-entry store buffer
• Push buffer
• Linefill buffer
• 32-bit address bus plus attributes and control
• Separate unidirectional 64-bit read data bus and 64-bit write data bus
• Supports cache line locking
• Supports way allocation
• Cache power usage can be minimized
3.1.3.6 BIU Features
The features of the e200z6 BIU are as follows:
• 32-bit address bus plus attributes and control
• Separate unidirectional 64-bit read data bus and 64-bit write data bus
• Overlapped, in-order accesses
3.1.4 Microarchitecture Summary
The e200z6 processor utilizes a seven stage pipeline for instruction execution. The instruction fetch 1,
instruction fetch 2, instruction decode/register file read, execute1, execute2/memory access1,
execute3/memory access2, and register writeback stages operate in an overlapped fashion, allowing single
clock instruction execution for most instructions.
The integer execution unit consists of a 32-bit arithmetic unit (AU), a logic unit (LU), a 32-bit barrel shifter
(shifter), a mask-insertion unit (MIU), a condition register manipulation unit (CRU), a count-leading-zeros
unit (CLZ), a 32 x 32 hardware multiplier array, result feed-forward hardware, and support hardware for
division.
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