Reset
MPC5566 Microcontroller Reference Manual, Rev. 2
4-6 Freescale Semiconductor
The following table describes the fields in the system reset control register (SIU_SRCR):
4.4 Functional Description
4.4.1 Reset Vector Locations
The reset vector contains a pointer to the instruction where code execution begins after BAM execution.
The address of the reset vector is specified by the boot mode, as listed in Table 4-4.
Table 4-3. SIU_SRCR Field Descriptions
Field Description
0
SSR
Software system reset. Writing a 1 to this bit causes an internal reset and assertion of the RSTOUT
pin. The
bit is automatically cleared by all reset sources except the software external reset.
0 Do not generate a software system reset.
1 Generate a software system reset.
1
SER
Software external reset. Writing a 1 to this bit causes an software external reset. The RSTOUT
pin is
asserted for a predetermined number of clock cycles (Refer to Section 4.2.2, “Reset Output (RSTOUT)”), but
the MCU is not reset. The bit is automatically cleared when the software external reset completes.
0 Do not generate an software external reset.
1 Generate an software external reset.
2–15 Reserved.
16
CRE
Checkstop reset enable
Writing a 1 to this bit enables a checkstop reset when the e200z6 core enters a checkstop state. The CRE
bit defaults to checkstop reset enabled. This bit is reset at POR.
0 No reset occurs when the e200z6 core enters a checkstop state.
1 A reset occurs when the e200z6 core enters a checkstop state.
17–31 Reserved.
Table 4-4. Reset Vector Locations
Boot Mode Reset Vector Location
External Boot 0x0000_0004 (0x0000_0000 is a valid RCHW)
Internal Boot Next word address after the first valid RCHW located. The BAM searches the lowest
address of each of the six low address space blocks in flash memory for a valid
RCHW. Hence, the available reset vector addresses are:
0x0000_0004
0x0000_4004
0x0001_0004
0x0001_C004
0x0002_0004
0x0003_0004
Serial Boot Specified over serial download
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