NXP Semiconductors MPC5566 - B.2 Calibration Bus

Calibration
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor B-3
B.2 Calibration Bus
The calibration bus is made up of address bus, data bus, bus control and clock signals. The calibration bus
is used by tools that include memory for calibration data or other code in development. Refer to Table B-1
for calibration bus signals. A 16-bit data bus and 19-bit address bus gives a basic addressing range of
1 MB. Alternatively, the maximum memory addressable using just one chip select is four MB.
Refer to Table B-2.
The VertiCal connector supports up to 4 chip select signals, although the actual number of chip selects
available depends on the device and package. Use the CAL_CS[0] chip select as the default calibration
chip select to ensure maximum portability of calibration tools across devices. The four calibration chip
select signals CAL_CS[0:3] are configured and function like the external chip select signals CS[0:3],
except the calibration chip selects have a higher priority in address decoding than the external chip selects,
CS[0:3]. Refer to Section B.8, “Application Information,” for application information on the number of
calibration chip selects.
The CAL_CS[0:3] chip selects have multiplexed signal functions to provide additional addressing bits that
allows the flexibility of increasing the addressing range or the number of chip selects. The calibration
functionality provides a calibration bus with pads that are in addition to the pads for the 416 pin package
part. Therefore, the calibration functionality does not use any I/O available in the 416 pin production
package for a calibration bus interface.
The P/A/G column in the following table differentiates each signal function that is multiplexed to the same
pin assignment. The P/A/G value is set in the PA field of the SIU_PCR registers and determines which
multiplexed signal function controls the pin. For more information on how to set the PA field, read the
Signals Chapter.
Table B-1. MPC5566 Calibration Bus Signals
496 VertiCal
Signal Name
Signal Function Signal Name P/A/G
Calibration Bus
CAL_CS[
0] Calibration chip select 0 CAL_CS[0] P
CAL_CS[1:3] Calibration chip select 1–3
Calibration address
CAL_CS[1:3]_
CAL_ADDR[9:11]
P
A
CAL_ADDR[12:30] Calibration address bus CAL_ADDR[12:30] P
CAL_DATA[0:15] Calibration data bus CAL_DATA[0:15] P
CAL_RD_WR Calibration read/write CAL_RD_WR P
CAL_WE/BE[0:1] Calibration write/byte enable CAL_WE/BE[0:1] P
CAL_OE Calibration output enable CAL_OE P
CAL_TS Calibration transfer start CAL_TS P
Clock Synthesizer
CLKOUT System Clock Output CLKOUT P