NXP Semiconductors MPC5566 - Page 793

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
18-36 Freescale Semiconductor
18.4.5.4 eTPU Channel Data Transfer Request Overflow Status Register
(ETPU_CDTROSR)
Data transfer request overflow status from all channels are grouped in ETPU_CDTROSR. The bits are
mirrored by the channels’ status/control registers. For more information on channel status registers and
data transfer request overflow, refer to Section 18.4.6.3, “eTPU Channel n Status Control Register
(ETPU_CnSCR),” and the eTPU Reference Manual.
NOTE
The host must write 1 to clear a data transfer request overflow status bit.
Address: Base + 0x0000_0220 (eTPU A)
Address: Base + 0x0000_0224 (eTPU B)
Access: R/W1c
0123456789101112131415
RCIOS
31
CIOS
30
CIOS
29
CIOS
28
CIOS
27
CIOS
26
CIOS
25
CIOS
24
CIOS
23
CIOS
22
CIOS
21
CIOS
20
CIOS
19
CIOS
18
CIOS
17
CIOS
16
W
w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RCIOS
15
CIOS
14
CIOS
13
CIOS
12
CIOS
11
CIOS
10
CIOS
9
CIOS
8
CIOS
7
CIOS
6
CIOS
5
CIOS
4
CIOS
3
CIOS
2
CIOS
1
CIOS
0
W
w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset0000000000000000
Figure 18-16. eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)
Table 18-17. ETPU_CIOSR Field Descriptions
Field Description
0–31
CIOSn
Channel n interrupt overflow status.
0 indicates that no interrupt overflow occurred in the channel.
1 indicates that an interrupt overflow occurred in the channel.
To clear a status bit, the host must write 1 to it.
For details about interrupts refer to the eTPU Reference Manual.