NXP Semiconductors MPC5566 - Page 774

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-17
Base + 0x0000_0400 ETPU_C0CR_A eTPU A channel 0 configuration register 32
Base + 0x0000_0404 ETPU_C0SCR_A eTPU A channel 0 status and control register 32
Base + 0x0000_0408
ETPU_C0HSRR_A
eTPU A channel 0 host service request
register
32
Base + 0x0000_040C — Reserved —
Base + 0x0000_0410 ETPU_C1CR_A eTPU A channel 1 configuration register 32
Base + 0x0000_0414 ETPU_C1SCR_A eTPU A channel 1 status and control register 32
Base + 0x0000_0418
ETPU_C1HSRR_A
eTPU A channel 1 host service request
register
32
Base + (0x0000_041C–0x0000_05EF) — Reserved —
Base + 0x0000_05F0 ETPU_C31CR_A eTPU A channel 31 configuration register 32
Base + 0x0000_05F4 ETPU_C31SCR_A eTPU A channel 31 status and control register 32
Base + 0x0000_05F8
ETPU_C31HSRR_A
eTPU A channel 31 host service request
register
32
Base + (0x0000_05FC–0x0000_07FF) — Reserved —
Base + 0x0000_0800 ETPU_C0CR_B
1
eTPU B channel 0 configuration register 32
Base + 0x0000_0804 ETPU_C0SCR_B
1
eTPU B channel 0 status and control register 32
Base + 0x0000_0808
ETPU_C0HSRR_B
1
eTPU B channel 0 host service request
register
32
Base + 0x0000_080C — Reserved —
Base + 0x0000_0810 ETPU_C1CR_B
1
eTPU B channel 1 configuration register 32
Base + 0x0000_0814 ETPU_C1SCR_B
1
eTPU B channel 1 status and control register 32
Base + 0x0000_0818
ETPU_C1HSRR_B
1
eTPU B channel 1 host service request
register
32
Base + (0x0000_081C–0x0000_09EC) — Reserved —
Base + 0x0000_09F0 ETPU_C31CR_B
1
eTPU B channel 31 configuration register 32
Base + 0x0000_09F4 ETPU_C31SCR_B
1
eTPU B channel 31 status and control register 32
Base + 0x0000_09F8
ETPU_C31HSRR_B
1
eTPU B Channel 31 host service request
register
32
Base + (0x0000_09FC–0x0000_7FFF) — Reserved —
Base + (0x0000_8000–0x0000_8BFF) SDM Shared Data Memory (parameter RAM) 4 KB
Base + (0x0000_8C00–0x0000_BFFF) — Reserved —
Base + (0x0000_C000–0x0000_CBFF) — SDM PSE mirror
2
4 KB
Base + (0x0000_CC00–0x0000_FFFF) — Reserved —
Table 18-5. Detailed Memory Map (continued)
Address Register Name Register Description Bits