NXP Semiconductors MPC5566 - Page 166

e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 3-31
Instruction
storage
IVOR 3 — SRR[0:1] • Access control.
• Precise external termination error and MSR[EE] = 1.
• Byte ordering interrupt due to:
• misaligned access across page boundary to pages with
mismatched VLE bits
• access to pages with VLE set
with E indicating little-endian.
• Misaligned instruction fetch interrupt when a flow changes
to an odd-halfword instruction boundary on a Book E
(non-VLE) instruction page, generated by the value of the
LR, CTR, or SRR0s field.
External input IVOR 4
2
EE, src SRR[0:1] External interrupt is asserted and MSR[EE]=1
Alignment IVOR 5 — SRR[0:1] • lmw, stmw not word aligned
• lwarx or stwcx. not word aligned
• dcbz with disabled cache or no cache present, or to W or I
storage
• SPE lD and ST instructions misaligned
Program IVOR 6 — SRR[0:1] Illegal, privileged, trap, FP enabled, AP enabled,
unimplemented operation
Floating-point
unavailable
IVOR 7 — SRR[0:1] MSR[FP]=0 and attempt to execute a Book E floating point
operation
System call IVOR 8 — SRR[0:1] Execution of the system call (sc) instruction
AP
unavailable
IVOR 9 — SRR[0:1] Unused by e200z6.
Decrementer IVOR 10 EE, DIE SRR[0:1] Decrementer timeout, and as specified in Book E: Enhanced
PowerPC
TM
Architecture, Rev 1.0, Ch. 8, pg. 194–195 and in
the e200Z6 PowerPC
tm
Core Reference Manual, Rev 0.
Fixed interval
timer
IVOR 11 EE, FIE SRR[0:1] Fixed-interval timer timeout and as specified in Book E:
Enhanced PowerPC
TM
Architecture, Rev 1.0, Ch. 8, pg.
195–196 and in the e200Z6 PowerPC
tm
Core Reference
Manual, Rev 0.
Watchdog
timer
IVOR 12 CE, WIE CSRR[0:1] Watchdog timeout: as specified in Book E: Enhanced
PowerPC
TM
Architecture, Rev 1.0, Ch. 8, pg. 196–197 and in
the e200Z6 PowerPC
TM
Core Reference Manual, Rev 0.
Data TLB
error
IVOR 13 — SRR[0:1] Data translation lookup did not match a valid entry in the TLB
Instruction
TLB error
IVOR 14 — SRR[0:1] Instruction translation lookup did not match a valid TLB entry
Table 3-11. Interrupts and Conditions (continued)
Interrupt
Type
Interrupt
Vector Offset
Register
Enables
1
Core Register
in Which
State
Information is
Saved
Causing Conditions