MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-13
Address: Base + 0x0004 Access: User read/write
0123 4 5 6789101112131415
R
PRESDIV RJW PSEG1 PSEG2
W
Reset
1
0000 0 0 0000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BOFF
MSK
ERR
MSK
CLK_
SRC
LPB
TWRN
MSK
RWRN
MSK
00
SMP
BOFF
REC
TSYN LBUF LOM PROPSEG
W
Reset
1
0000 0 0 0000000000
1
CANx_CR is unaffected by soft reset (which occurs when CAN_MCR[SOFTRST] is asserted).
Figure 22-4. Control Register (CANx_CR)
Table 22-8. CANx_CR Field Descriptions
Bits Description
0–7
PRESDIV[0:7]
Prescaler division factor. Defines the ratio between the CPI clock frequency and the serial clock (SCK)
frequency. The SCK period defines the time quantum of the CAN protocol. For the reset value, the SCK
frequency is equal to the CPI clock frequency. The maximum value of this register is 0xFF, that gives a
minimum SCK frequency equal to the CPI clock frequency divided by 256. For more information, see
Section 22.4.5.4, “Protocol Timing.”
8–9
RJW[0:1]
Resync jump width. Defines the maximum number of time quanta
1
that a bit time can be changed by one
re-synchronization. The valid programmable values are 0–3.
10–12
PSEG1[0:2]
Phase segment 1. Defines the length of phase buffer segment 1 in the bit time. The valid programmable
values are 0–7.
13–15
PSEG2[0:2]
Phase segment 2. Defines the length of phase buffer segment 2 in the bit time. The valid programmable
values are 1–7.
16
BOFFMSK
Bus off mask. Provides a mask for the bus off interrupt.
0 Bus off interrupt disabled
1 Bus off interrupt enabled
17
ERRMSK
Error mask. Provides a mask for the error interrupt.
0 Error interrupt disabled
1 Error interrupt enabled
18
CLK_SRC
CAN engine clock source. Selects the clock source to the CAN Protocol Interface (CPI) to be either the
system clock (driven by the PLL) or the crystal oscillator clock. The selected clock is fed into the prescaler
to generate the serial clock (SCK).
0 = The CAN engine clock source is the oscillator clock
1 = The CAN engine clock source is the system clock
S-clock frequency
CPI clock frequency
PRESDIV 1+
-----------------------------------------------------=
Resync Jump Width RJW + 1=
Phase Buffer Segment 1 PSEG1 + 1()Time Quanta×=
Phase Buffer Segment 2 PSEG2 + 1()Time Quanta×=
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