NXP Semiconductors MPC5566 - Page 681

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-2 Freescale Semiconductor
Figure 17-1 shows the block diagram of the eMIOS.
Figure 17-1. eMIOS Block Diagram
Read note 1
[D][A]
Counter
buses
(time
bases)
EMIOS16
EMIOS_Flag_Out16
[C][A]
[B][A]
•
•
•
•
•
•
Counter
buses
(time
bases)
Counter
buses
(time
bases)
All
submodules
Internal
counter
clock
enable
STAC
Internal
output disable input[0:3]
Global time
base enable in
Global time
base enable out
System
clock
Enhanced Modular
Unified
STAC client submodule
BIU
Slave
interface
Clock
prescaler
Output disable
control bus
Note 1: Connection between UC[n-1] and UCn necessary to implement QDEC mode.
Input/Output
•
•
•
•
•
•
•
•
•
•
•
•
Subsystem
channel
23
EMIOS23
EMIOS_Flag_Out23
Unified
channel
16
Unified
channel
15
EMIOS15 (Read note 2)
EMIOS_Flag_Out15
Unified
channel
8
Unified
channel
7
Unified
channel
0
EMIOS8
EMIOS_Flag_Out8
EMIOS7
EMIOS_Flag_Out7
EMIOS0
EMIOS_Flag_Out0
EMIOS_Flag_Out8
EMIOS_Flag_Out9
EMIOS_Flag_Out10
EMIOS_Flag_Out11
EMIOS_Flag_Out[20:23]
ETPUA_ODI3
ETPUA_ODI2
ETPUA_ODI1
ETPUA_ODI0
ETPUB_ODI[0:3]
bus
Note 2: On channels 12–15, there is no input from EMIOS[12:15], only from the DSPI module.