Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-10 Freescale Semiconductor
5
MTFE
Modified timing format enable. Enables a modified transfer format to be used.
See Section 20.4.7.4, “Modified Transfer Format Enabled (MTFE = 1) with Classic SPI Transfer Format Set
(CPHA = 1) for SPI and DSI.”
0 Modified SPI transfer format disabled
1 Modified SPI transfer format enabled
6
PCSSE
Peripheral chip select strobe enable. Enables the PCSx[5]_PCSS
to operate as a PCS strobe output signal.
See Section 20.4.6.5, “Peripheral Chip Select Strobe Enable (PCSS).”
0PCSx[5]_PCSS
is used as the peripheral chip select 5 signal
1PCSx[5] _PCSS
is used as an active-low PCS strobe signal
7
ROOE
Receive FIFO overflow overwrite enable. Enables an RX FIFO overflow condition to ignore the incoming
serial data or to overwrite existing data. If the RX FIFO is full and new data is received, the data from the
transfer that generated the overflow is ignored or put in the shift register.
If the ROOE bit is set, the incoming data is put in the shift register. If the ROOE bit is cleared, the incoming
data is ignored. See Section 20.4.9.6, “Receive FIFO Overflow Interrupt Request (RFOF).”
0 Incoming data is ignored
1 Incoming data is put in the shift register
8–9 Reserved, but implemented. These bits are writable, but have no effect.
10–15
PCSISn
Peripheral chip select inactive state. Determines the inactive state of the PCSx[n] signal.
You must configure PCSx[0]_SS
as inactive high for slave mode operation.
0 The inactive state of PCSx[n] is low
1 The inactive state of PCSx[n] is high
16 Reserved
17
MDIS
Module disable. Allows the clock to stop to non-memory mapped logic in the DSPI, effectively putting the
DSPI in a software controlled power-saving state. The reset value of the MDIS bit is parameterized, with a
default reset value of 0. See Section 20.4.10, “Power Saving Features.”
0 Enable DSPI clocks
1 Allow external logic to disable DSPI clocks
18
DIS_TXF
Disable transmit FIFO. Enables and disables the TX FIFO. When the TX FIFO is disabled, the transmit part
of the DSPI operates as a simplified double-buffered SPI. See Section 20.4.3.3, “FIFO Disable Operation for
details.”
0 TX FIFO is enabled
1 TX FIFO is disabled
19
DIS_RXF
Disable receive FIFO. Enables and disables the RX FIFO. When the RX FIFO is disabled, the receive part of
the DSPI operates as a simplified double-buffered SPI. See Section 20.4.3.3, “FIFO Disable Operation for
details.”
0 RX FIFO is enabled
1RX FIFO is disabled
Table 20-3. DSPIx_MCR Field Descriptions (continued)
Field Description
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