NXP Semiconductors MPC5566 - Page 691

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-12 Freescale Semiconductor
The following table describes the fields in the eMIOS channel B data register:
Table 17-8. EMIOS_CADRn, EMIOS_CBDRn, and EMIOS_ALTAn Value Assignments
Operating Mode
Register Access
Write Read Write Read
Alternate
Read
GPIO A1, A2 A1 B1,B2 B1 —
SAIC
1
—A2B2B2—
SAOC
1
1
In these modes, the register EMIOS_CBDRn is not used, but B2 can be accessed.
A2 A1 B2 B2 —
IPWM — A2 — B1 —
IPM — A2 — B1 —
DAOC A2 A1 B2 B1 —
PEA A1 A2 — B1 —
PEC
1
A1 A1 B1 B1 A2
QDEC
1
A1 A1 B2 B2 —
WPTA A1 A1 B1 B1 A2
MC – normal
1
A2 A1 B2 B2 —
MC – buffered A2 A1 B2 B2 —
OPWFM – normalA2A1B2B1—
OPWFM – buffered A2 A1 B2 B1 —
OPWMC – normal A2 A1 B2 B1 —
OPWMC – buffered A2 A1 B2 B1 —
OPWM – normal A2 A1 B2 B1 —
OPWM – buffered A2 A1 B2 B1 —