Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-64 Freescale Semiconductor
Enabling continuous SCK disables the PCS to SCK delay and the After SCK delay. The delay after transfer
is fixed at one SCK cycle. Figure 20-41 shows timing diagram for continuous SCK format with continuous
selection disabled.
Figure 20-41. Continuous SCK Timing Diagram (CONT= 0)
If the CONT bit in the TX FIFO entry is set or the DCONT in the DSPIx_DSICR is set, PCS remains
asserted between the transfers when the PCS signal for the next transfer is the same as for the current
transfer. Figure 20-42 shows timing diagram for continuous SCK format with continuous selection
enabled.
Figure 20-42. Continuous SCK Timing Diagram (CONT=1)
SCK
(CPOL = 0)
PCS
SCK
(CPOL = 1)
Master SOUT
t
DT
t
DT
= 1 SCK.
Master SIN
SCK
(CPOL = 0)
PCS
SCK
(CPOL = 1)
Master SOUT
Master SIN
Transfer 1 Transfer 2
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