Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-65
command before SDS is asserted. Only commands of CFIFOs that have the ABORT_ST bit asserted can
be scheduled in this manner. Under such conditions:
1. A CFIFO0 command is scheduled for the next transmission independently of the type of data that
was previously scheduled. The time during which SDS is negated is stretched to allow the eQADC
to load the CFIFO0 command and start its transmission.
2. CFIFO1-5 commands are only scheduled for the next transmission if the previously scheduled data
was a null message. The time during which SDS is negated is stretched to allow the eQADC to load
that command and start its transmission. However, if the previously scheduled data was a
command, no rescheduling occurs and the next transmission starts without delays.
If a CFIFO becomes triggered while SDS is negated, but the eQADC only attempts to reschedule that
CFIFO command after SDS is asserted, then the current transmission is aborted depending on if the
conditions for that are met or not.
Figure 19-37. CFIFO Prioritization Logic
ADC0
Command Buffer0
(2 Entries)
eQADC
Prioritization
Logic
Prioritization
for ADC0
Usage
Command
6 x Command
Command
CFIFO0
Command
CFIFO1
Command
CFIFO2
Command
CFIFO3
Command
CFIFO4
Command
CFIFO5
ADC1
Command Buffer1
(2 Entries)
Prioritization
for ADC1
Usage
Command
EQADC SSI
Transmit Buffer
Prioritization
for EQADC
SSI Usage
Command
(1 Entry)
eQADC SSI
Serial Link
External Device
SSI Interface
Command Buffer2
ADC2
Command
Command Buffer3
ADC3
Command
External
Device
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