Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 11-13
Address: Base + 0x0000 Access: User R/W
0123456789101112131415
R0
PREDIV MFD
0
RFD
LOC
EN
LOL
RE
LOC
RE
W
Reset0000000100010000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DIS
CLK
LOL
IRQ
LOC
IRQ
RATE DEPTH EXP
W
Reset0000000000000000
Figure 11-8. Synthesizer Control Register (FMPLL_SYNCR)
Table 11-4. FMPLL_SYNCR Field Descriptions
Field Description
0 Reserved.
1–3
PREDIV
[0:2]
The PREDIV bits control the value of the divider on the input clock. The output of the pre-divider circuit
generates the reference clock (F
prediv
) to the FMPLL analog loop. When the PREDIV bits are changed, the
FMPLL immediately loses lock. To prevent an immediate reset, the LOLRE bit must be cleared before writing
the PREDIV bits. In 1:1 (dual-controller) mode, the PREDIV bits are ignored and the input clock is fed directly
to the analog loop.
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101–111 Invalid values
Note: Programming a PREDIV value such that the ICO operates outside its specified range causes
unpredictable results and the FMPLL does not lock. Refer to the device Data Sheet for details on the
ICO range.
Note: To avoid unintentional interrupt requests, disable LOLIRQ before changing PREDIV and then reenable
it after acquiring lock.
Note: When using crystal reference mode or external reference mode, The PREDIV value must not be set
to any value that causes the phase/frequency detector to go below 4 MHz. That is, the crystal
(F
ref_crystal
) or external clock (F
ref_ext
) frequency divided by the PREDIV value creates the F
prediv
frequency that must be greater than or equal to 4–20 MHz. Refer to the device Data Sheet for F
prediv
values.
Note: To use the 8–20 MHz OSC, the PLL predivider must be configured for divide-by-two operation by tying
PLLCFG[2] low (set PREDIV to 0b000).
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